发明名称 POLYSILICON GATE DOPING LEVEL VARIATION FOR REDUCED LEAKAGE CURRENT
摘要 <p>A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.</p>
申请公布号 WO2003044855(A2) 申请公布日期 2003.05.30
申请号 US2002036236 申请日期 2002.11.12
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址