| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory in which redundancy relieving efficiency is high, increment of a test time is suppressed, and of which a manufacturing cost is low. SOLUTION: In a row decoder connected to a memory cell array 1 in which memory cells are arranged in a matrix state, the decode is provided with a decoding circuit 42 receiving an input address, generating a selection signal for selecting a specific word line in the memory cell array 1, and generating a selection signal for a word line by a word line batch selection signal 36 also, a first driver circuit 44 receiving an output of the decoding circuit 42 and having small driving capability for driving word lines, and a second driver circuit 45 having big driving capability, and a driver control circuit 43 making the second driver circuit 45 having big driving capability non-activation by a driver control signal.</p> |
