GENERATION OF COMPRESSION TEST PLAN FOR TESTING INTEGRATED CIRCUIT, AND TEST SERIES GENERATION AND TEST

摘要

PROBLEM TO BE SOLVED: To reduce the scale of a circuit to be added for a test by reducing a test series length in a strong possibility inspection DFT method. SOLUTION: The test plan of each circuit element for composing a data path is subjected to scheduling in parallel in a form to be compressed, and a compression operation is made to generate a compression test plan (step 1006). A test series is generated by substituting the test pattern of each circuit element into the compression test plan.