| 摘要 |
<p>A transistor comprising a p-type semiconductor substrate (12) provided with a projection (13a) having a pair of opposed sides (13b, 13b), a gate insulating film (15c), a pair of n-type source/drain regions (BL1, BL2), a tunnel insulating film (15a), a pair of floating gates (FG1, FG2), an interpolysilicon film, and a control gate (CG). The concentration of the p-type impurities in the root portion of the projection (13a) connecting linearly the source/drain regions (BL1, BL2) is higher than that in the other portion than the root portion. An erase voltage for erasing the accumulated charge in the floating gate (FG) is applied between the control gate (CG) and the source/drain regions (BL1, BL2) to allow an erase current flowing to the control gate (CG) or the source/drain regions (BL1, BL2), thereby erasing the accumulated charge.</p> |
