发明名称 |
Semiconductor integrated circuit device |
摘要 |
A clock signal generating circuit supplies a clock signal output in a short time of 2-3 clock periods after operation starts. As a result, the clock signal generating circuit can be stopped simultaneously when the operation of an internal circuit is put in a stop state, the clock signal generating circuit can output a clock signal when the internal circuit returns to the operating state, and power consumption when the internal circuit is in the stop state is reduced. A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed-to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.
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申请公布号 |
US2003098730(A1) |
申请公布日期 |
2003.05.29 |
申请号 |
US20020322594 |
申请日期 |
2002.12.19 |
申请人 |
MIYAZAKI MASAYUKI;TATEZAWA KEN;TAKADA KIWAMU;UCHIYAMA KUNIO;NISHII OSAMU;HASEGAWA KIYOSHI;AOKI HIROKAZU;KOKUBO MASARU |
发明人 |
MIYAZAKI MASAYUKI;TATEZAWA KEN;TAKADA KIWAMU;UCHIYAMA KUNIO;NISHII OSAMU;HASEGAWA KIYOSHI;AOKI HIROKAZU;KOKUBO MASARU |
分类号 |
G06F1/04;G06F1/06;G06F1/32;H01L21/82;H01L21/822;H01L27/04;H03L7/07;H03L7/081;H03L7/099;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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