| 摘要 |
<p>The invention provides circuitry for carrying out an arithmetic operation requiring a plurality of iterations. The circuitry comprises N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry comprises at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry. <IMAGE></p> |
