WAFER LEVEL CHIP SCALE PACKAGE HAVING STUD BUMP AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A wafer level chip package having a stud bump and a fabricating method thereof are provided to prevent a crack due to the stress by removing a slope portion from a redistribution line pattern formed on a layer between a solder bump and a chip pad. CONSTITUTION: A passivation layer(110) and a chip pad(115) are formed on a silicon substrate(100). A stud bump(125') is formed on the chip pad of the silicon substrate. The stud bump is surround by the first insulating layer(135'). A redistribution line pattern(140) is formed on the same horizontal plane of the first insulating layer and the stud bump in order to connect the stud bump with a solder bump(160). The second insulating layer(150) is used for insulating the redistribution line pattern. The solder bump is formed on the exposed redistribution line pattern.