| 摘要 |
PROBLEM TO BE SOLVED: To reduce variance in the output voltage of a depletion MOS reference voltage circuit in a semiconductor integrated circuit device mounted with a submicron CMOS integrated circuit and the depletion MOS reference voltage circuit. SOLUTION: When ions are injected into a channel area so as to suppress short-channel effects, one or both of depletion NMOS transistor 4 and an enhanced NMOS transistor 5 constituting the depletion MOS reference voltage circuit are shielded by a mask to prevent impurity ions from being injected into them, and consequently one or both of the depletion NMOS transistor 4 and enhanced NMOS transistor 5 do not have a punch-through stopper layer.
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