| 摘要 |
A plurality of groups of first flip-flops (group 40 of flip-flops A1-An-1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1-Bn for each of channels CIA-CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA-CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.
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