| 摘要 |
<p>A process for fabricating a dual charge storage location, electrically programmable memory cell, comprising: forming a first dielectric layer (101) over a semiconductor material layer (103;503;603) of a first conductivity type; forming a charge trapping material layer (105) over the first dielectric layer; selectively removing the charge trapping material layer from over a semiconductor material layer region (112;304) intended to act as a central channel region for the memory cell, so to leave two charge trapping material layer portions at the sides of the central channel region; masking the central channel region and selectively implanting dopants of a second conductivity type into the semiconductor material layer to form memory cell source/drain regions (117;311) at the sides of the two charge trapping material layer portions; forming a second dielectric layer (121;203;315) over the charge trapping material layer; and forming a polysilicon gate (129;323) over the second dielectric layer, the polysilicon gate being superimposed over the central channel region and the two charge trapping material layer portions. <IMAGE> <IMAGE> <IMAGE></p> |
