发明名称 |
Semiconductor die package with improved thermal and electrical performance |
摘要 |
A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.
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申请公布号 |
US6566749(B1) |
申请公布日期 |
2003.05.20 |
申请号 |
US20020050428 |
申请日期 |
2002.01.15 |
申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
JOSHI RAJEEV;SAPP STEVEN |
分类号 |
H01L21/60;H01L23/04;H01L23/367;(IPC1-7):H01L23/10;H01L23/34 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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