发明名称 Clock shaping circuit and electronic equipment
摘要 In a clock shaping circuit, a phase comparator 31, a selector 76, a loop filter 2, and a VCSO/VCXO 4 form a PLL circuit's main feedback loop during normal operation. When the main feedback loop of the PLL circuit malfunctions due to unlocking, a quartz crystal oscillator circuit is used, and a PLL circuit's backup feedback loop is established, which includes a backup phase comparator 74, the selector 76, the loop filter 2, and the VCSO/VCXO 4.
申请公布号 US2003090305(A1) 申请公布日期 2003.05.15
申请号 US20020286418 申请日期 2002.11.01
申请人 KOBAYASHI YOSHIHIRO;IMAI NOBUYUKI 发明人 KOBAYASHI YOSHIHIRO;IMAI NOBUYUKI
分类号 H03B5/30;H03B5/02;H03B5/12;H03B5/26;H03B5/32;H03L7/087;H03L7/095;H03L7/099;H03L7/14;H03L7/18;(IPC1-7):H03L7/06 主分类号 H03B5/30
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