发明名称 |
Method of and apparatus for timing verification of LSI test data and computer product |
摘要 |
Timing verification of the LSI test data is performed as follows. In test synthesis, a script text for static timing analysis (STA) is generated together with a test circuit. The STA script text is used to perform static timing analysis. Function verification is performed between a netlist generated through the test synthesis and a timing-verified netlist based on the static timing analysis. The function-verified netlist is released to a production division, and the netlist is used to automatically generate a test pattern by an automatic test pattern generation (ATPG) tool. A netlist comprising test vectors for automatic test equipment is acquired from the generated ATPG pattern.
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申请公布号 |
US2003093729(A1) |
申请公布日期 |
2003.05.15 |
申请号 |
US20020253713 |
申请日期 |
2002.09.25 |
申请人 |
FUJITSU LIMITED |
发明人 |
SUZUKI MASAHITO;SHIMIZU RYUJI |
分类号 |
G01R31/28;G01R31/3183;G06F11/263;G06F17/50;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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