Multiplexor generating a glitch free output when selecting from multiple clock signals

摘要

A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.