| 摘要 |
A clock modulation circuit modulates the frequency of a clock signal to generate a modulated clock signal. A wait requesting signal receives frequency information indicating the frequency of the modulated clock signal and, when the frequency information indicates a frequency higher than a reference frequency, generates a wait requesting signal to an external bus interface. Since an optimum wait cycle is inserted to the external bus interface according to a change of the frequency of the modulated clock signal, needless wait cycle can be prevented from being inserted to the external bus interface. As a result of this, it is possible to disperse the peak of radiated noise which is caused by the clock signal and to reduce electromagnetic interference, without decreasing performance of a system. Namely, it can serve both market needs for reducing noise and speeding up.
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