发明名称 INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To restrain latchup of an active element and to provide an integrated circuit, wherein characteristics of an inductor are improved by restraining generation of eddy current in an integrated circuit having an active element such as a CMOS and an inductor, and to provide its manufacturing method. SOLUTION: In an integrated circuit, a semiconductor substrate 2 whose P<-> type or P<--> type resistivity is 10 to 1000Ω.cm is provided, a CMOS 5 is provided on the semiconductor substrate 2, a insulation layer 22 wherein several steps of wirings are buried is provided on the CMOS 5 and an inductor 23 is provided in a region off on the CMOS 5 on the insulation layer 22. A p<+> type diffusion layer 3 whose resistivity is about 0.01Ω.cm is provided between the semiconductor substrate 2 and the CMOS 5.
申请公布号 JP2003133430(A) 申请公布日期 2003.05.09
申请号 JP20010322267 申请日期 2001.10.19
申请人 NEC CORP 发明人 OKUBO HIROAKI;NAKASHIBA YASUTAKA
分类号 H01L21/822;H01L21/8234;H01L21/8238;H01L27/04;H01L27/06;H01L27/08;H01L27/092;(IPC1-7):H01L21/823;H01L21/823 主分类号 H01L21/822
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