| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay circuit which is simple circuit composition and increase precision of delay time. SOLUTION: The delay circuit provides a plurality of delay blocks 1a, 1b and 1c which are cascade connected, and they respectively have a 1st complementary input terminals to which 1st complementary signals are input, a 2nd complementary input terminals to which 2nd complementary signals are input, and a complementary output terminals which select either the 1st or the 2nd complementary signals by logic of a delay selection signal, and delay the signals and output a 3rd complementary signals. The complementary output signals of the delay blocks are connected to the 2nd complementary input terminals of the next delay block except the last stage, the complementary output terminals of the last delay block output complementary delay signals that is delayed the 1st complementary signals according to the logic of the delay selection signal, and the 1st commentary signals are input in common to the each 1st complementary input terminals of a plurality of delay blocks. By this invention, the delay quantity can be adjusted in the unit of one gate stage, therefore, the precision of delay time can be increased than before.</p> |
