HIGH VOLTAGE BIT/COLUMN LATCH FOR VCC OPERATION

摘要

A bit/column latch (200) comprising a pair of first (m1, m2) and second (m3, m4) cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter (m1, m2) has the source o its NMOS transistor coupled to ground via a control transistor (m6) and has its output connected to the associated bit line (3). When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a 'low' to storing a 'high'. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.