| 摘要 |
<p>A method of designing integrated circuits having an hierarchical structure for quiescent current testing comprises analyzing each of one or more selected hierarchical blocks independently of other selected blocks to identify any circuit states of each block which could result in elevated quiescent current levels during quiescent current testing of the circuit, the analysis beginning with blocks at a lowest level of hierarchy and proceeding in sequence through each level of design hierarchy to a highest level of hierarchy containing a top-level block; and calculating a fault coverage for each selected block.</p> |
