| 摘要 |
A phase noise reduction system of a frequency synthesizer for obtaining an arbitrary frequency oscillation by locking a reference oscillation frequency of a reference oscillator to an oscillation frequency of a voltage controlled oscillator has a variable frequency divider for voltage controlled oscillator which divides an oscillation frequency of the voltage controlled oscillator, a variable frequency divider for reference oscillator which divides a reference oscillation frequency of the reference oscillator, and a lock detection section which initially sets a common small number of frequency division to the variable frequency divider for voltage controlled oscillator and the variable frequency divider for reference oscillator, respectively, subsequently detects locking of frequency, and switches the setting of number of frequency division from the small number of frequency division to a larger number of frequency division. The phase noise reduction system is capable of switching to a state of better phase noise in a shorter period of time thus enabling a high-speed locking.
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