| 摘要 |
A system-on-a-chip with a variable clock rate bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively adjusts the clock rate of the bus based on the timing value. The bus controller may also examine the transfer size value or a priority value, and further determine a minimum rate of transfer required to provide the bandwidth on the bus to meet the time frame within which the requested transfer should occur. The integrated circuit may further comprises a power control device coupled to or part of the bus controller, which monitors power consumption and provides power conservation information to the bus controller. The bus controller may further adjust usage of the bus in response to the power conservation information provided by the power control device. The bus may be a time division, multiple access (TDMA) bus. The bus controller may enable data transfers on the TDMA bus only during assigned time slots of assigned frequency and assigned length. The bus controller may also further adjust assignment of the TDMA bus in response to the power conservation information.
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