| 摘要 |
An output buffer circuit includes first and second MOS transistors connected in series between a power supply and ground, a first pull up transistor coupled between the power supply and a gate of the first MOS transistor, a first pull down transistor coupled between ground and the gate of the first MOS transistor, a second pull up transistor coupled between the power supply and the gate of the second MOS transistor, a second pull down transistor coupled between ground and the gate of the second MOS transistor, a slew-rate control node, a third MOS transistor coupled between the power supply and the slew-rate control node, a fourth MOS transistor coupled between ground and the slew-rate control node, a first variable resistance provided between the first pull up and pull down transistors, and a second variable resistance provided between the second pull up and pull down transistors.
|
