发明名称 Apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits
摘要 An exemplary method for simulating the effect of mismatch in design flows comprises receiving measured data, receiving an original model, extracting a mismatch model based on the measured data and the original model, attaching the mismatch model to the netlist to obtain a modified netlist, and simulating an effect of mismatch based on the modified netlist. In one embodiment, the extracting of a mismatch model includes selecting a set of model parameters, generating a distribution of mismatch values for each of the model parameters, extracting a set of linking coefficients based on said mismatch values, and extracting said mismatch model based on said set of linking coefficients. In another embodiment, the attaching of the mismatch model to the netlist includes determining a number of layers in the netlist, generating a copy of a lower layer in the netlist, the copy including a reference to a mismatch model definition, generating a copy of a higher layer in the netlist, replacing a reference to the lower layer in the higher layer by a reference to the copy of the lower layer, and generating a new model definition.
申请公布号 US6560755(B1) 申请公布日期 2003.05.06
申请号 US20000648396 申请日期 2000.08.24
申请人 CADENCE DESIGN SYSTEMS INC 发明人 ZHANG XISHENG;CHEN JAMES CHIEH-TSUNG;LIU ZHIHONG;XIE JUSHAN;PANG XUCHENG;FANG JINGKUN
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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