MANUFACTURE OF TRENCH-GATE FIELD-EFFECT TRANSISTORS

摘要

A vertical power trench-gate field-effect transistor has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25). While an n-type drift layer (14) still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode pad (25). The channel profiles of the device are optimised by providing the p-type regions (15A) after the trench insulation (17), and voltage breakdown at the bottom corners of the trenches (20) is suppressed by providing the p-type regions (15B) in the inactive area (200).