发明名称 BUS TO SYSTEM MEMORY DELAYED READ PROCESSING
摘要 A method to operate a computer system bridge circuit includes enqueueing multiple delayed read requests to system memory, where each delayed read request is associated with a different expansion bus devices. The method may also include forwarding a second enqueued read request to the system memory before receiving a response to a first forwarded enqueued read request. The method may further include arbitrating to an expansion bus device (having an enqueued delayed read request) only after read data is received from the system memory in response to a forwarded read request. A computer system incorporating a bridge circuit operated in accordance with the described method is also described.
申请公布号 US2003084223(A1) 申请公布日期 2003.05.01
申请号 US19990386808 申请日期 1999.08.31
申请人 JEDDELOH JOSEPH M. 发明人 JEDDELOH JOSEPH M.
分类号 G06F13/40;(IPC1-7):G06F13/00;G06F13/14 主分类号 G06F13/40
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