发明名称 |
Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, LSI designing method, and gate extraction method |
摘要 |
A method of extracting timing characteristics from transistor circuit data of modularity design products (a module) such as a CPU core in which the extracted timing characteristics are used for the timing verification of a circuit including a module to be extracted and timing constraints when logical synthesis or timing-driven layout is made. Particularly, since conditions fit for a timing rule of the module are included in timing characteristics when timing verification is executed by simulation, verification free of pseudo error is enabled. Also, the configuration of a timing characteristic library, a storage medium storing it and an LSI designing method using the storage medium are provided.
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申请公布号 |
US6557150(B1) |
申请公布日期 |
2003.04.29 |
申请号 |
US20000485169 |
申请日期 |
2000.02.07 |
申请人 |
HITACHI, LTD. |
发明人 |
HONMURA TETSUROO;NAKAJIMA TAKASHI;GOTO KENZO;WATANABE SHOICHI |
分类号 |
G06F17/50;(IPC1-7):G06K17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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