发明名称 INFORMATION PROCESSOR AND METHOD, RECORDING MEDIUM, AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To make a system including a PLL circuit entering a deadlock state speedily recover to its normal state without troubling a user. SOLUTION: In a step S1, it is decided whether a VCO input voltage is within a reference range. When so, it is decided in a step S2 whether the PLL circuit is locked. When the PLL circuit is locked, a VCO output signal is used as a clock. When the PLL circuit is not locked, a through clock is used. When a state in which the VCO input voltage is not within the reference ranges lasts for longer than a specific time, a deadlock state is decide in a step S5. If it is not decided in a step S6 that the deadlock state successively exceeds the number of times, the PLL circuit is made to recover in a step S7. When it is decided the deadlock state exceeds the specified number of times, the fault of the PLL circuit is reported to the user in a step S8.
申请公布号 JP2003124807(A) 申请公布日期 2003.04.25
申请号 JP20010314811 申请日期 2001.10.12
申请人 SONY CORP 发明人 TSUMORI HIROKI
分类号 H03L7/095 主分类号 H03L7/095
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