| 摘要 |
PROBLEM TO BE SOLVED: To suppress the lowering of the surge withstand voltage of an output circuit due to an increase in the potential of a power supply line occurring at the time of ESD test of a semiconductor integrated circuit device. SOLUTION: The semiconductor integrated circuit device comprises a pad 1 for external connection, an electrostatic discharge protective circuit 2, an output circuit 3, an output buffer circuit 4, an output signal fixing circuit 19, and an internal circuit 21. The output signal fixing circuit 19 has a first capacitor 19a and a second capacitor 19b and is arranged such that the output signal from a second prebuffer circuit 18 can be fixed to an 'L' level even if the output from the internal circuit 21 is not settled. Since the output signal from the second prebuffer circuit 18 reaches the 'L' level by the output signal fixing circuit 19 at the time of ESD test, an NMIS transistor 12 is turned off, thus preventing a surge current from concentrating in the NMIS transistor 12.
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