发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR MEMORY USING THIS CIRCUIT
摘要 PROBLEM TO BE SOLVED: To increase the operation speed of a decoding circuit by making circuit constitution requiring no decoder control signalΦ2 out of a control signalΦ1 of an address buffer and a control signalΦ2. SOLUTION: The above mentioned purpose is achieved by uniting an address buffer and a decoder and by providing such a constitution that an output current path of a decoding output is connected in series to a transistor constituting the address buffer and the decoder. When this decoding circuit is used for a semiconductor memory, the access time can be increased, power consumption can be reduced, and the number of cycles can be increased.
申请公布号 JP2003123480(A) 申请公布日期 2003.04.25
申请号 JP20010316182 申请日期 2001.10.15
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 KANETANI KAZUO;NANBU HIROAKI
分类号 G11C11/413;G11C8/10;G11C11/34;H03K19/096;(IPC1-7):G11C11/413 主分类号 G11C11/413
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