Semiconductor integrated circuit device e.g. double data rate SRAM has delay lock loop circuit with phase detector detecting phase difference of outputs of two buffers to change output tap of delay circuits

摘要

A multiplexer (35A) outputs signal with rising edge and falling edges based on the output of delay circuits (21,22,31,32). A delay lock loop (DLL) circuit (3) has phase detector (33) detecting phase difference of outputs of input buffer and buffer (38). A counter (34) outputs a signal to change output tap of the circuits (31,32) based on detector output. An Independent claim is also included for delay lock loop apparatus.