发明名称 REDUCING OUTPUT CAPACITANCE OF DIGITAL-TO-TIME DOMAIN CONVERTER FOR VERY HIGH FREQUENCY DIGITAL WAVEFORM SYNTHESIS
摘要 <p>In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signals from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.</p>
申请公布号 WO2003034253(A1) 申请公布日期 2003.04.24
申请号 US2002033566 申请日期 2002.10.17
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