发明名称 DEVICE FOR GENERATING CLOCK SIGNAL FOR DECODER
摘要 PROBLEM TO BE SOLVED: To provide a device which generates a decoder clock signal for decoding a data signal which is obtainable together with a clock signal and a data word signal for signal notification of data words both capable of having mutually different frequency. SOLUTION: This device has a phase control circuit (1) which receives a clock signal and supplies a decoder clock signal from its output part, and further which is equipped with at least one adjustable divider (14) to be preferably placed at the input part of itself and having an adjustable division rate. This device is equipped with a detector (2) which decides at least the ratio of the frequency of the clock signal to the frequency of the data word signal and adjusts the division rate within an adjustable divider (14) based on this frequency ratio, so that the frequency of the decoder clock signal may have a fixed specified frequency ratio to the frequency of the data word signal in any case of frequency ratios capable of occurring between clock signals and data word signals.
申请公布号 JP2003115759(A) 申请公布日期 2003.04.18
申请号 JP20020186264 申请日期 2002.06.26
申请人 KONINKL PHILIPS ELECTRONICS NV 发明人 MOEHLMANN ULRICH
分类号 G06F1/08;H03K5/26;H03L7/08;H03L7/18 主分类号 G06F1/08
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