发明名称 IMAGE PROCESSOR AND IMAGE PROCESSING METHOD
摘要 <p>PROBLEM TO BE SOLVED: To enable to reduce processing load. SOLUTION: A host CPU 41 stores a PAT (program association table) packet, a PMT (program map table) packet, and a DIT (discontinuity information table) packet to be inserted to an extracted TS (transport stream) into an insertion packet buffer 91. The host CPU 41 outputs a control signal to open a gate 92 to a changeover switch 93 in a timing of inserting the DIT packet. A comparison section 94 outputs the control signal to open the gate 92 to a changeover switch 93 for every period when the PAT packet or the PMT packet is inserted. The changeover switch 93 selects the received control signal and outputs it to a gate 92 to open the gate 92. A packet insertion section 82 reads the packet from the insertion packet buffer 91 to insert it to the extracted TS.</p>
申请公布号 JP2003111038(A) 申请公布日期 2003.04.11
申请号 JP20010306253 申请日期 2001.10.02
申请人 SONY CORP 发明人 ADACHI HIROSHI
分类号 H04J3/00;H04N5/44;H04N7/08;H04N7/081;H04N7/173;H04N7/20;H04N21/235;H04N21/435;H04N21/647;(IPC1-7):H04N7/08 主分类号 H04J3/00
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