| 摘要 |
PROBLEM TO BE SOLVED: To reduce a logic synthesis and layout work by optimizing a hierarchy (module) for RTL description. SOLUTION: A composite block in which the logics of a combinational circuit and a non-combinational circuit coexist is analyzed, and the logic of the non- combinational circuit is extracted (S102), and the extracted non-combinational circuit is replaced with the cell of an RTL library prepared in advance whose logic is the same as that of the extracted non-combinational circuit (S106).
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