| 摘要 |
<p>The invention uses basic pipeline/subranging architecture to provide a circuit for analogue to digital conversion comprising: a sample and hold circuit (1); a coarse analogue to digital converter (2); a digital to analogue converter (3); combining logic circuitry; a fine analogue to digital converter (6); and also a voltage to current converter (7; R1); means for subtracting in the current domain, preferably comprising a means for summing at a virtual earth node (9); and means for converting current to voltage (10; R2) at the input to the fine analogue to digital converter (6). The fine analogue to digital converter (6) preferably additionally comprises a resistor (R3) matched to the means for converting current to voltage (10; R2), and a current source matched to the current to the digital to analogue converter (3). A plurality of pairs of voltage to current (7A; 7B) and current to voltage 10A; 10B converters may be connected in cascade formation and a plurality of sample and hold circuits (1) are provided. This has the advantage of increasing the sample rate of the circuit. An implementation according to the invention, enables a reduction in the number of components to be matched as well as the degree of matching and provides an ADC with high speed and high resolution without the disadvantages of the known implementations.</p> |
