A THIN-LAYER SILICON-ON-INSULATOR (SOI) HIGH-VOLTAGE DEVICE STRUCTURE

摘要

A thin layer SOI high-voltage device (100) in which the drift charge is depleted using a three-dimensional MOS capacitor structure (10). The drift region of the high-voltage semiconductor device is doped with a graded charge profile which increases from source-to-drain. The drift region is physically patterned to create a stripe geometry where individual SOI stripes (16a, 16b). Each SOI stripe (16a and 16b) is individually circumscribed longitudinally by a dielectric layer (22a, 22b) wherein each dielectric layer (22a, 22b) is longitudinally circumscribed by field platesof a conducting multi-capacitor field plate layer (30) which is electrically shorted to the substrate (12). The resultant structure is a thin drift-region stripe which is completely enclosed by a MOS field plate, resulting in three-dimensional depletion upon application of a bias voltage between the SOI stripe (16a and 16b) and its encapsulating field plates.