发明名称 |
Digitally controllable internal clock generating circuit of semiconductor memory device and method for same |
摘要 |
An internal clock generating circuit of a semiconductor device includes: a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock; a thermometer for outputting a thermometer code value in response to an input selection data; a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value of the thermometer; and a pulse regenerator for outputting an adjusted internal clock by restoring a pulse form of the clock output from the multiplexer into its original state and controlling the delay thereof as much as desired.
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申请公布号 |
US2003067338(A1) |
申请公布日期 |
2003.04.10 |
申请号 |
US20020041060 |
申请日期 |
2002.01.07 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM NAM-SEOG;YOON YONG-JIN |
分类号 |
G06F13/42;G06F1/06;G06F1/12;G11C7/22;H03K5/14;H03L7/00;(IPC1-7):G06F1/04 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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