Method and apparatus of testing memory device power and ground pins in an array assembly platform

摘要

An apparatus and technique for performing continuity tests of power and ground pins on a packaged integrated circuit. The technique includes using a first and second fanout circuit each including a number of signal paths. Each signal path includes a switch and corresponds to a power or ground socket on a board configured to hold a number of integrated circuit packages. The fanout circuits allow full device testing, as well as testing of individual pins. By controlling the state of the switches, power and ground may be selectively supplied to power and ground pins to check the continuity of the signals from the integrated circuit device within the package to the external pins provided to route the signal to an external device.