Defective address storage scheme for memory device

摘要

A defective address storage circuit reduces current consumption in a memory device by utilizing a fuse block having address storage blocks arranged in series. Each address storage block preferably has two portions, each portion having a fuse and transistor. A NAND-type architecture can be implemented by arranging the portions of each block in parallel while the fuse and transistor are arranged in series, or by arranging the portions of each block in series while the fuse and transistor are arranged in parallel.