| 摘要 |
Hold time methods, systems, and computer program products are implemented to ensure that storage elements in a circuit have sufficient hold times without detrimentally affecting cycle times for other paths in the circuit. Electric circuits are designed by determining which storage elements have hold-time deficiencies, and by inserting an appropriate time delay element in a selected path preceding the storage element, or at a source or destination storage element, without exceeding a predetermined cycle time in a second path that overlaps the first path, for at least one storage element in an electrical circuit. The invention simulates insertion of the time delay element before or after a logic element that precedes a storage element that has a hold-time deficiency. The invention determines which storage elements and which circuit paths between adjacent storage elements are subject to hold time deficiencies, assembles a hold time deficiency list, and determines whether a selected hold-time-deficient storage element can be preceded with a delay element without violating a cycle time constraint in another cycle path. The invention further includes determining the placement of a delay element in a storage system having a network of storage elements interconnected with logic elements by using a criterion that protects cycle times in other storage element paths with slower signal propagation. The method further includes modifying a net list of storage and logic element interconnections to include insertion of one or more time delay elements.
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