| 摘要 |
A scan flip-flop (100A) that may operate as a positive flip-flop or a negative flip-flop in a normal operating mode has been disclosed. Scan flip-flop (100A) may include a master latching circuit (11), a slave latching circuit (12), and a clock circuit (13A). Clock circuit (13A) may receive a signal (XA), a control signal (control), and a mode signal (SCN). Signal (XA) may select between a positive flip-flop operation and a negative flip-flop operation when in a normal operating mode. Mode signal (SCN) may select between a normal operating mode and a scan test mode. Control signal (control) may disable signal (XA) so that scan flip-flop (100A) may operate in a known mode, such as a positive flip-flop, regardless as to the value of signal (XA). Scan flip-flop (100A) may reduce logic gates in clock lines which may be required in a conventional approach.
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