发明名称 |
Content addressable memory having cascaded sub-entry architecture |
摘要 |
A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.
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申请公布号 |
US2003065880(A1) |
申请公布日期 |
2003.04.03 |
申请号 |
US20020286206 |
申请日期 |
2002.11.01 |
申请人 |
GORDON TARL S.;NADKARNI RAHUL K. |
发明人 |
GORDON TARL S.;NADKARNI RAHUL K. |
分类号 |
G11C15/04;G11C15/00;(IPC1-7):G06F12/00;G06F12/14;G06F13/00;G06F13/28 |
主分类号 |
G11C15/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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