On-line cancellation of sampling mismatch in interleaved sample-and-hold circuits

摘要

The present invention relates to a high speed sample and hold circuit having a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also having a calibration sample and hold subcircuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a timing for one or more of the plurality of sample and hold subcircuits to thereby reduce sampling mismatch between the plurality of sample and hold subcircuits. The present invention also having a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.