Method and apparatus for direct digital synthesis of frequency signals

摘要

A frequency signal generator (300) generates a desired output signal Fout (365) based on the ratio of the frequency a reference clock signal (301) to that of the desired output signal (Fclk/Fout)=N+R, where the N is an integer portion and R is a fractional portion of the ratio. A counter (320) generates a counter overflow signal based on counting a minimum of N transitions of the reference clock signal. An accumulator (330) accumulates the fractional portion R in response to the counter overflow signal (325), and outputs the accumulated value (335) that is preferably used as address information for selecting one of a number of delay paths (340, 350) for outputting the desired output signal.