| 摘要 |
Arbitration for a bus mastership is performed in accordance with the priority degrees of data which are to be transferred on a bus, by a comparatively simple construction. In a case where interfaces 2, 3 simultaneously output to the bus 1 the priority degrees which correspond to non-ATM lines 6, 7 being the reception sources or transmission destinations of the data stored in ATM cells, and where the priority degrees outputted by the interface themselves are the highest, the interfaces transmit to the bus 1, bus mastership request signals which contain the addresses of the interfaces themselves. A bus control module 4 receives the bus mastership request signals on the bus 1, it determines that one of the interfaces to which the bus mastership is granted, and it outputs to the bus 1 a bus mastership grant signal which contains the address of the determined interface.
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