发明名称 Semiconductor integrated circuit device
摘要 P-type well regions Ap1 and Ap9 on which first and second pre-charge circuits are formed, and p-type well regions Ap2, Ap3, Ap7 and ap8 on which first and second Y-switch circuits are formed, are formed on both ends of a sense amplifier formation region, respectively. A bit line BL2T, which extends from a first memory cell formation region of first and second memory cell formation regions arranged in both sides of the sense amplifier formation region, arrives at a p-type well region An1 on which a sense amplifier is formed, via both a p-type well region Ap1 on which the first pre-charge circuit is formed and p-type well regions Ap2 and Ap3 on which the Y-switch circuit is formed. Therefore, a wiring region c for arranging wirings other than bit lines can be secured on the extended bit line BL2T.
申请公布号 US6538946(B2) 申请公布日期 2003.03.25
申请号 US20010897919 申请日期 2001.07.05
申请人 HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. 发明人 ARAI KOUJI;MIYATAKE SHINICHI
分类号 H01L21/8242;G11C7/02;G11C7/18;G11C11/4091;H01L27/108;(IPC1-7):G11C7/02 主分类号 H01L21/8242
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