发明名称 CIRCUIT INTEGRE COMPRENANT UN CIRCUIT DE BROUILLAGE DE DONNEES ENREGISTREES DANS UNE ZONE MEMOIRE VOLATILE
摘要 The invention concerns an integrated circuit (MP2) comprising a volatile storage area (DTMEM) whereof the content has a specific value after the integrated circuit has been reset, the volatile storage area being connected to a data bus (DTB) via an encryption circuit (JMCT) coding data recorded in the storage area and decoding data read in the storage area, the data being coded at least in accordance with a key (Ks) applied to the encryption circuit. The invention is characterised in that the key applied to the encryption circuit is a random key delivered by a random signal generator (RGEN) designed to modify the value of the key at least each time the integrated circuit is reset.
申请公布号 FR2818845(B1) 申请公布日期 2003.03.21
申请号 FR20000016747 申请日期 2000.12.21
申请人 STMICROELECTRONICS SA 发明人 WUIDART SYLVIE
分类号 G06F1/00;G06F21/00;(IPC1-7):H04L9/18;G06F12/14 主分类号 G06F1/00
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