| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce cross talk between bit lines and between bit lines and upper layer wirings or lower layer wirings, in a semiconductor integrated circuit comprising a SRAM. SOLUTION: A semiconductor integrated circuit is provided with a plurality of memory cells having at least a first port and a second port respectively, bit lines of a first group intersecting mutually at a first position between memory cells of each column, bit lines of a second group intersecting mutually at a second position between memory cells of each column, first word lines for selecting one memory cell in a first port of memory cells of each column, second word lines for selecting one memory cell in a second port of memory cells of each column, a write-in circuit writing data in a memory cell selected by a first word line, and a read-out circuit reading out differentially data stored in a memory cell selected by the second word line.</p> |
