| 摘要 |
PROBLEM TO BE SOLVED: To provide a bit line decoder scheme selecting one memory cell comprising two storage site in a dual bit memory cell array. SOLUTION: The bit line decorder scheme is provided that connects data and voltage to a plurality of bit lines at the dual bit flash memory array. The bit liens are connected to a plurality of intermediate data lines by a first decoding unit, the intermediate data lines are connected to a plurality of data lines of sense amplifiers by a second decoding unit. In one embodiment, voltage is connected to a selected bit line through a separate decoding unit, in a second embodiment, the voltage is connected to through the decoding unit connected to the intermediate data line. |
