发明名称 VERIFICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To surely perform verification of non-coincidence of an input about an analog circuit in a semiconductor integrated circuit in which a digital circuit and the analog circuit exist mixedly. SOLUTION: On the basis of layout information and circuit diagram information, coincidence of the layout of semiconductor integrated circuit and a circuit diagram is verified by comparison (S1-S3). On the basis of the layout information or the circuit diagram information, a first transistor to be connected with a prescribed power source, and a second transistor to be connected in series with the first transistor are detected (S4). On the basis of the layout information or the circuit diagram information, data (e.g. channel lengths L1, L2) concerning each channel of both of the detected transistors are extracted (S5). The extracted data concerning each channel are compared with each other, and it is decided whether the connection order of both transistors is right on the basis of the comparison, thereby performing a process corresponding to the decided result (S6-S9).
申请公布号 JP2003086686(A) 申请公布日期 2003.03.20
申请号 JP20010277114 申请日期 2001.09.12
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 TOMIOKA KOJI;SATO NORIYUKI;MOGI TOMOYUKI
分类号 G01R31/316;G06F17/50;H01L21/82;(IPC1-7):H01L21/82 主分类号 G01R31/316
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